ISCAS 2002

Abstract:

Business as usual will lead to kilowatts of power consumption in high performance microprocessors. Design strategies must change and new circuit techniques must be employed to get around this power wall without compromising performance goals. Excessive leakage currents, parameter variation, clock power and interconnect delays will be the key bottlenecks. Circuit design techniques to control leakage power during active operation, burn-in and standby will be discussed. Techniques to reduce impact of within-die and die-to-die variations on processor frequency and power be elucidated. Clock power reductions achievable by dual-edge-triggered flipflops will be illustrated. Leakage-tolerant, high performance datapath circuits and architectures will be described. Circuits techniques to improve delays of long on-chip interconnects will be presented.

Topics:

1. Technology and design challenges for low power and high performance
2. Low power design techniques with leakage control and variation tolerance
3. High performance circuits and interconnects with leakage tolerance

About the Presenter:

Vivek De is a Principal Engineer and Manager of Low Power Circuit Technology at Microprocessor Research of Intel Labs in Hillsboro, Oregon. He received his Ph.D. in Electrical Engineering from Rensselaer Polytechnic Institute, Troy, New York in 1992. He served as Technical Program Chair of 2001 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'01), General Chair of ISLPED'02 and Technical Program Chair of 2002 ACM Great Lakes Symposium on VLSI. He is the guest editor of a special issue on low power electronics for IEEE Transactions on VLSI Systems. He is the recipient of a best paper award at the 1996 IEEE International ASIC Conference in Portland, Oregon.

Ram K. Krishnamurthy received his Ph.D. degree in Electrical & Computer Engineering from Carnegie Mellon University, Pittsburgh, PA, in 1998, where his thesis research was focused on low-power DSP circuit design. Since graduation, he has been with Intel Corporation's Microprocessor Research Labs in Hillsboro, Oregon, where he is presently leading the high-performance and low-voltage circuits research group. He serves on Intel's SRC review committee and the ASIC, CICC, and ISCAS program committees.

Siva Narendra is a staff engineer at Intel Labs. He has been with Intel Labs for the past 5 years where his research focuses on low voltage analog and digital circuits. He received his Ph.D. in Electrical Engineering and Computer Science from MIT in 2002. He is an associate editor for the IEEE Transactions on VLSI Systems.