Click on a session's title to view the contents of the session.
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| Sunday Morning, May 23 |
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08:30 - 11:30
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| Tutorial: TUT-1: Design of Continuous-Time Filters from 0.1 Hz to 2.0 GHz |
Junior Ballroom C
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| Tutorial: TUT-4: Low Power Video Platforms for Mobile Applications |
Port McNeil
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| All Day Sunday, May 23 |
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08:30 - 16:15
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| Tutorial: TUT-9: Microsystems and Nanotechnology Through Applications |
Port Alberni
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| Tutorial: TUT-10: Ultrawideband Radio Communications |
Junior Ballroom D
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| Sunday Afternoon, May 23 |
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13:15 - 16:15
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| Tutorial: TUT-5: Design for Testability of Analog and Mixed-Signal Integrated Circuits |
Junior Ballroom C
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| Tutorial: TUT-6: Clocking and Synchronization issues in sub-100nm System on Chip (SoC) Designs |
Junior Ballroom A
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| Tutorial: TUT-7: Cryptography: Circuits and Systems Approach |
Junior Ballroom B
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| Tutorial: TUT-8: CMOS Imagers: From Phototransduction to Image Processing |
Port McNeil
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| Sunday, May 23 2004 |
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16:30 - 18:00
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| Forum: FORUM-1: New Era of Technology |
Junior Ballroom
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| Monday, May 24 |
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08:00 - 09:00
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| Plenary: Genomic Signal Processing |
Grand Ballroom
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09:30 - 11:00
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| ASP-L1: Pipelined ADC |
Grand Ballroom A
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| ASP-L2: Analog Filtering Techniques I |
Grand Ballroom B
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| ASP-L3: Voltage References |
Grand Ballroom C
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| COMM-L1: Communication Architectures |
Grand Ballroom D
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| VLSI-L1: Low Power Circuits and Architecture |
Junior Ballroom A/B
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| VLSI-L2: Video |
Junior Ballroom C
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| DSP-L1: FIR Digital Filters |
Junior Ballroom D
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| PSEC-L1: Power Integrated Circuits |
Finback
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| CAD-L1: Placement and Routing I |
Galiano
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| NLCS-L1: Oscillators Design and Implementation |
Granville
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| SEN-L1: Image Sensors I |
Orca
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| MMSA-L1: Advanced Multimedia Systems: End-to-End Frameworks |
Port Alberni
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| Invited Session: INV-1: Spiking Neural Networks I |
Port Hardy
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| Invited Session: INV-2: Ultra Wideband Systems |
Port McNeill
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| COMM-P1: Communication Architectures and Systems I |
Poster Area 1
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| CAD-P1: CAD for Analog and Mixed Signal Circuits |
Poster Area 2
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| DSP-P1: Digital Filters |
Poster Area 3
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| DSP-P2: Digital Signal Processing I |
Poster Area 4
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| ASP-P1: Analog Circuits in Systems I |
Poster Area 5
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| ASP-P2: Analog Circuits in Systems II |
Poster Area 6
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| VSPC-P1: 3-D and Image Processing |
Poster Area 7
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| MMSA-P1: Data Hiding and Watermarking Techiques for Multimedia Systems |
Poster Area 8
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| MMSA-P2: Intelligent Processing Techniques for Multimedia Systems and Applications |
Poster Area 9
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| VLSI-P1: Low Power Design and Implementation I |
Poster Area 10
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11:15 - 12:45
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| ASP-L4: Pipelined and Folded ADC |
Grand Ballroom A
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| ASP-L5: Analog Filtering Techniques II |
Grand Ballroom B
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| ASP-L6: Broadband and UWB circuits |
Grand Ballroom C
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| COMM-L2: CDMA Systems |
Grand Ballroom D
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| VLSI-L3: Low Power Arithmetic |
Junior Ballroom A/B
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| VLSI-L4: MPEG |
Junior Ballroom C
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| DSP-L2: IIR Digital Filters |
Junior Ballroom D
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| PSEC-L2: Power Converter Control |
Finback
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| CAD-L2: Placement and Routing II |
Galiano
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| NLCS-L2: PLLs Design, Implementation and Application |
Granville
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| SEN-L2: Vision Sensors |
Orca
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| MMSA-L2: Multimedia Watermarking and Data Hiding |
Port Alberni
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| Invited Session: INV-3: Spiking Neural Networks II |
Port Hardy
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| Invited Session: INV-4: Multirate Systems for Communications |
Port McNeill
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| COMM-P2: Communication Circuits Design I |
Poster Area 1
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| CAD-P2: CAD for Digital Circuits |
Poster Area 2
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| DSP-P3: Digital Filters and Filter Banks |
Poster Area 3
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| DSP-P4: Digital Signal Processing II |
Poster Area 4
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| NLCS-P1: Nonlinear Circuits Analysis and Design I |
Poster Area 5
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| NLCS-P2: Nonlinear Circuits Analysis and Design II |
Poster Area 6
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| VSPC-P2: General Image and Video Processing I |
Poster Area 7
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| MMSA-P3: Communication and Coding Techniques for Multimedia Systems |
Poster Area 8
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| MMSA-P4: VLSI/SOC Implementation for Multimidia Sytems II |
Poster Area 9
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| VLSI-P2: Low Power Design and Implementation II |
Poster Area 10
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14:15 - 15:45
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| ASP-L7: Flash ADC |
Grand Ballroom A
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| ASP-L8: Analog Signal Processing I |
Grand Ballroom B
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| ASP-L9: Oscillators |
Grand Ballroom C
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| COMM-L3: Ultra Wide Band Systems |
Grand Ballroom D
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| VLSI-L5: Low Power Buses and Circuits |
Junior Ballroom A/B
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| VLSI-L6: Image Processing |
Junior Ballroom C
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| DSP-L3: Digital Filters |
Junior Ballroom D
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| PSEC-L3: Power Amplifiers |
Finback
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| CAD-L3: Analog Modeling, Synthesis & Optimization I |
Galiano
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| NLCS-L3: Chaos-based Methodologies for Security |
Granville
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| SEN-L3: Mems and Sensory Systems |
Orca
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| MMSA-L3: Multimedia Database and Retrieval Systems |
Port Alberni
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| ASP-L10: Circuit Theory in Electronics |
Port Hardy
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| Invited Session: INV-5: Digital Signal Processing for Smart Multi-Media Systems |
Port McNeill
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| COMM-P3: Computation Kernels and IP for Communication Systems I |
Poster Area 1
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| CAD-P3: Testing, Verification, and Simulation |
Poster Area 2
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| DSP-P5: Discrete-Time Transforms and Wavelets |
Poster Area 3
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| DSP-P6: Digital Signal Processing III |
Poster Area 4
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| CNN-P1: Circuit Design for Array Computers |
Poster Area 5
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| ASP-P3: Controlled Amplifiers |
Poster Area 6
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| ASP-P4: Current Amplifiers |
Poster Area 7
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| ASP-P5: Analog Filtering I |
Poster Area 8
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| ASP-P6: Analog Filtering II |
Poster Area 9
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| VSPC-P3: General Image and Video Processing II |
Poster Area 10
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16:00 - 17:30
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| ASP-L11: CMOS ADC |
Grand Ballroom A
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| ASP-L12: Analog Signal Processing II |
Grand Ballroom B
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| ASP-L13: Mixed Signal Testing |
Grand Ballroom C
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| COMM-L4: Oscillator Design |
Grand Ballroom D
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| VLSI-L7: Low Power Codes and Cryptography |
Junior Ballroom A/B
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| VLSI-L8: Coding |
Junior Ballroom C
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| DSP-L4: Digital Filter Banks |
Junior Ballroom D
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| PSEC-L4: Multilevel Power Converters |
Finback
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| CAD-L4: Analog Modeling, Synthesis & Optimization II |
Galiano
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| ASP-L14: General Circuit Theory |
Granville
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| SEN-L4: Chemical, Acoustic, Olfactory and Neuromorphic Sensors |
Orca
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| MMSA-L4: Multimedia Communication and Transmission |
Port Alberni
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| Invited Session: INV-6: Silicon Implementations of CNN and Programmable Mixed-Signal Vision I |
Port Hardy
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| Invited Session: INV-7: Nonlinear Dynamics and Complexity in Network Traffic Modeling and Control |
Port McNeill
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| |
| Monday, May 24 2004 |
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17:45 - 19:15
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| Forum: FORUM-2: The Future of Circuits and Systems |
Junior Ballroom
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| Tuesday, May 25 |
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08:00 - 09:00
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| Plenary: CNN Technology for Brain-like Spatial-Temporal Sensory Computing - Present and Future |
Grand Ballroom
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09:30 - 11:00
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| ASP-L15: Current-Steering DAC |
Grand Ballroom A
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| ASP-L16: Bioinspired Circuits |
Grand Ballroom B
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| ASP-L17: Voltage and Current Sources I |
Grand Ballroom C
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| COMM-L5: Phase Locked Loops (PLL) Circuits and Architectures |
Grand Ballroom D
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| VLSI-L9: High Performance Low Power |
Junior Ballroom A/B
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| VLSI-L10: Arithmetic |
Junior Ballroom C
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| DSP-L5: Digital Signal Processing Applications I |
Junior Ballroom D
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| PSEC-L5: Systems Theory for Power |
Finback
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| CAD-L5: Digital Circuits Synthesis & Optimization |
Galiano
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| NLCS-L4: Nonlinear Dynamics and Chaos in Communications I: Modulation and Coding |
Granville
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| VSPC-L1: Motion Estimation |
Orca
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| MMSA-L5: Multimedia Coding and Segmentation |
Port Alberni
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| Invited Session: INV-8: Bionics and Theory of Cellular Neural Networks |
Port Hardy
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| Invited Session: INV-9: Current Challenges in Mixed-Signal/RF Design and CAD |
Port McNeill
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| VLSI-P3: Video IP Cores |
Poster Area 1
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| CAD-P4: New Ideas in Physical Design |
Poster Area 2
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| NSA-P1: Neural Systems and Applications II |
Poster Area 3
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| SEN-P1: Network Sensors and MEMS |
Poster Area 4
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| VSPC-P4: Image and Video Compression |
Poster Area 5
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| DSP-P7: Digital Signal Processing for Communications |
Poster Area 6
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| ASP-P7: Analog Circuits and Technology I |
Poster Area 7
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| ASP-P8: Analog Circuits and Technology II |
Poster Area 8
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| VLSI-P5: VLSI Architectures |
Poster Area 9
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| VLSI-P4: Arithmetic Module Implementation |
Poster Area 10
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11:15 - 12:45
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| ASP-L18: Digital-to-Analog Converters |
Grand Ballroom A
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| ASP-L19: Design Techniques for ASP |
Grand Ballroom B
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| ASP-L20: Voltage and Current Sources II |
Grand Ballroom C
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| COMM-L6: Decoding for Communication Systems |
Grand Ballroom D
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| VLSI-L11: SoC Design Technology |
Junior Ballroom A/B
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| VLSI-L12: Adders and Multipliers |
Junior Ballroom C
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| DSP-L6: Digital Signal Processing Applications II |
Junior Ballroom D
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| CNN-L1: Bio-inspired and Neuromorphic Array Computers |
Finback
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| CAD-L6: Mixed Signal Circuit and Device Modeling |
Galiano
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| NLCS-L5: Nonlinear Dynamics and Chaos in Communications II: Coding and Traffic |
Granville
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| VSPC-L2: Video over Networks |
Orca
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| MMSA-L6: Multimedia Understanding and Recognition |
Port Alberni
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| Invited Session: INV-10: Frequency-Response Masking Techniques |
Port Hardy
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| Invited Session: INV-11: Recent Advances in the Control of Power Electronics |
Port McNeill
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| COMM-P4: Communication Circuits Design II |
Poster Area 1
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| PSEC-P2: Control of Power Converters |
Poster Area 2
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| PSEC-P3: Power Electronics Circuits |
Poster Area 3
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| SEN-P2: Neuromorhic and Sensory Systems |
Poster Area 4
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| BIO-P1: Biomedical Circuits and Systems I |
Poster Area 5
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| DSP-P8: Digital Signal Processing IV |
Poster Area 6
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| ASP-P9: Testing of Mixed Signal Circuits |
Poster Area 7
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| ASP-P10: Mixed Signal and Sensor Interface Circuits |
Poster Area 8
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| PSEC-P4: Analysis of Power Systems |
Poster Area 9
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| PSEC-P1: Power Electronics and Systems |
Poster Area 10
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14:15 - 15:45
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| ASP-L21: Sigma-Delta Converters I |
Grand Ballroom A
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| ASP-L22: Filter Applications |
Grand Ballroom B
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| ASP-L23: Sensor Interface Circuits |
Grand Ballroom C
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| COMM-L7: Circuits for Communications |
Grand Ballroom D
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| VLSI-L13: Noise in Digital Circuits |
Junior Ballroom A/B
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| VLSI-L14: Turbo and Viterbi Algorithms |
Junior Ballroom C
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| DSP-L7: Multidimensional Signal Processing I |
Junior Ballroom D
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| CNN-L2: Implementation of CNNs and Array Computers |
Finback
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| CAD-L7: Interconnect and Clock Distribution |
Galiano
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| NLCS-L6: Nonlinear Circuits Modelling |
Granville
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| VSPC-L3: Transcoding |
Orca
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| MMSA-L7: Multimedia Systems and Applications: Advanced Techniques |
Port Alberni
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| Invited Session: INV-12: Information Assurance and Data Hiding I |
Port Hardy
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| DSP-L8: Adaptive Signal Processing I |
Port McNeill
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| COMM-P5: Computation Kernels and IP for Communication Systems II |
Poster Area 1
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| NSA-P2: Neural Network Circuits and Systems II |
Poster Area 2
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| VLSI-P7: Arithmetic and Cryptography |
Poster Area 3
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| SEN-P3: Image Sensors II |
Poster Area 4
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| DSP-P9: Digital Signal Processing V |
Poster Area 5
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| ASP-P11: RF Circuits I |
Poster Area 6
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| ASP-P12: RF Circuits II |
Poster Area 7
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| NLCS-P3: Nonlinear Circuits and Systems Analysis and Application I |
Poster Area 8
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| NLCS-P4: Nonlinear Circuits and Systems Analysis and Application II |
Poster Area 9
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| VLSI-P6: Arithmetic and DSP Implementation |
Poster Area 10
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16:00 - 17:30
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| ASP-L24: Sigma-Delta Converters II |
Grand Ballroom A
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| ASP-L25: High Gain Amplifiers |
Grand Ballroom B
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| ASP-L26: Mixed Signal Circuits |
Grand Ballroom C
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| COMM-L8: Optical Communication |
Grand Ballroom D
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| VLSI-L15: Interconnect |
Junior Ballroom A/B
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| VLSI-L16: Cryptography |
Junior Ballroom C
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| DSP-L9: Multidimensional Signal Processing II |
Junior Ballroom D
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| CNN-L3: Complex Spatio-temporal Dynamics in Multi-layer CNNs |
Finback
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| CAD-L8: Fundamentals of CAD Algorithms |
Galiano
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| NLCS-L7: Modelling and Analysis of Nonlinear Systems |
Granville
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| VSPC-L4: Advanced Video Coding |
Orca
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| MMSA-L8: VLSI/SOC Implementation for Multimedia Systems I |
Port Alberni
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| Invited Session: INV-13: Heterogeneous Systems |
Port Hardy
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| DSP-L10: Adaptive Signal Processing II |
Port McNeill
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| Wednesday, May 26 |
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08:00 - 09:00
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| Plenary: Practical Applications of 3-D and 4-D Filters |
Grand Ballroom
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09:30 - 11:00
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| ASP-L27: ADC Circuits |
Grand Ballroom A
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| ASP-L28: High Speed Amplifiers |
Grand Ballroom B
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| ASP-L29: RF Frontend Circuits |
Grand Ballroom C
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| COMM-L9: Frequency Synthesizers |
Grand Ballroom D
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| VLSI-L17: I/O Circuits |
Junior Ballroom A/B
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| VLSI-L18: Field Programmable and Reconfigurable |
Junior Ballroom C
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| DSP-L11: Digital Signal Processing |
Junior Ballroom D
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| CNN-L4: Analysis and Applications of CNNs |
Finback
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| CAD-L9: Verification, Testing, and Validation |
Galiano
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| NLCS-L8: Nonlinear Circuits Analysis and Design |
Granville
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| VSPC-L5: Encoder Optimization |
Orca
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| BIO-L1: Implantable Electronics |
Port Alberni
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| Invited Session: INV-14: Advances in Speech Processing with Applications |
Port Hardy
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| DSP-L12: Digital Signal Processing for Communications I |
Port McNeill
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| COMM-P6: Wireless Systems and High Speed Systems |
Poster Area 1
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| ASP-P13: Analog Circuits I |
Poster Area 2
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| ASP-P14: Analog Circuits II |
Poster Area 3
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| ASP-P15: High-Frequency Amplifiers II |
Poster Area 4
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| ASP-P16: Data Converters II |
Poster Area 5
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| ASP-P17: Data Converters III |
Poster Area 6
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| BSP-P1: Blind Signal Processing II |
Poster Area 7
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| VLSI-P9: FPGA and PLA |
Poster Area 8
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| VLSI-P10: Image Processing and Implementation |
Poster Area 9
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| VLSI-P8: Circuit Design I |
Poster Area 10
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11:15 - 12:45
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| ASP-L30: Analog-to-Digital Converters |
Grand Ballroom A
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| ASP-L31: High-Frequency Amplifiers I |
Grand Ballroom B
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| ASP-L32: RF Power Amplifiers |
Grand Ballroom C
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| COMM-L10: Receivers Architecture and Design |
Grand Ballroom D
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| VLSI-L19: Clocking |
Junior Ballroom A/B
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| VLSI-L20: Memory |
Junior Ballroom C
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| DSP-L13: Implementation of DSP Algorithms |
Junior Ballroom D
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| NSA-L1: Neural Network Algorithms and Architectures |
Finback
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| CAD-L10: New Areas in CAD I |
Galiano
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| NLCS-L9: Switching Circuits and Systems: Bifurcation Analysis and Control |
Granville
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| VSPC-L6: Scalable Video Coding |
Orca
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| BIO-L2: Medical Sensors and Amplifiers |
Port Alberni
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| Invited Session: INV-15: Behavioral Modeling and Analog and Mixed Signal Simulation |
Port Hardy
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| DSP-L14: Digital Signal Processing for Communications II |
Port McNeill
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| GTC-P1: Graph Algorithms and Applications II |
Poster Area 1
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| ASP-P18: Analog Circuits III |
Poster Area 2
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| ASP-P19: Analog Circuits IV |
Poster Area 3
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| CNN-P2: Applications of Cellular Neural Networks and Array Computers |
Poster Area 4
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| ASP-P20: Sigma-Delta Converters III |
Poster Area 5
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| ASP-P21: Sigma-Delta Converters IV |
Poster Area 6
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| BSP-P2: Blind Signal Processing III |
Poster Area 7
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| NEGS-P1: Nanoelectronics and Nanoarchitecture |
Poster Area 8
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| VLSI-P12: Array Architecture and SoC |
Poster Area 9
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| VLSI-P11: Circuit Design II |
Poster Area 10
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14:15 - 15:45
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| ASP-L33: Data Converters I |
Grand Ballroom A
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| ASP-L34: Operational Amplifiers |
Grand Ballroom B
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| ASP-L35: Signal Processing Building Blocks I |
Grand Ballroom C
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